1. Field of the Invention
The invention lies in the field of techniques for making neighboring wells implanted with dopant ions of differing conductivity type in VLSI complementary MOS field effect transistor (CMOS) circuits.
2. Prior Art
A method of the prior art is disclosed by European Patent Application No. 0 081 804.
Modern CMOS processes are double-well processes (n-wells and p-wells) and are described in detail in, for example, IEEE Trans. on Electron Devices, ED-30 (1983), Pages 1339-1344 and in IEDM Technical Digest 1984, 15.4, pages 410-413. The production of the two wells is achieved by using separate masks or by using only one mask in a self-adjusting "double well" process execution.
The disadvantage of the self-adjusted double-well process is that a compensated region is inherently produced at the well edges or boundaries due to the three-dimensional overlap of the well dopings. The size and compensation degree thereof have a direct influence on the latch-up susceptibility of the CMOS structure, or, alternatively on the minimum possible n.sup.+ /p.sup.+ spacing. The consequential effect of the compensated region is to limit the penetration depth x.sub.j of the well to relatively small values. As a consequence of the high current densities, or, alternatively, of the higher surface-proximate current component, sensitivity of the well MOSFETs to substrate currents (forward-biasing of the source diode) increases. Moreover, the junction capacitances are comparatively high since the overall charge in the well is determined by the requirements on the breakdown voltage U.sub.CEO and by the basic numer of the parasitic bipolar transistor. Therefore, the necessary high doping concentrations for shallow wells.